Computer System and Organisation

The evolution of electronic computing is categorized into distinct generations characterized by the underlying switching technology, memory architecture, and programming paradigms:

Proposed by mathematician and physicist John von Neumann in 1945, the Von Neumann architecture introduced the revolutionary concept that both program instructions and data reside in the same physical, addressable memory space. Prior to this, mechanical calculators required tedious physical rewiring to alter their operational tasks.

The classical Von Neumann architecture consists of three interconnected subsystems:

• Central Processing Unit (CPU): The computational brain executing instructions and directing the entire machine.
• Main Memory Unit: A linear sequence of numbered memory locations holding both executable binary instructions and operand data.
• Input/Output (I/O) Subsystem: Interfaces enabling interaction with human operators and external peripheral hardware.

The Central Processing Unit contains two primary functional processing units and a bank of ultra-fast internal registers:

• Arithmetic Logic Unit (ALU): Performs all elementary arithmetic calculations (addition, subtraction, multiplication, division) and logical decisions (bitwise AND, OR, NOT, XOR, magnitude comparisons like equal, greater than, less than). The ALU updates a dedicated Status / Flags Register containing indicator bits such as Zero Flag (Z), Carry Flag (C), Sign Flag (S), and Overflow Flag (V).
• Control Unit (CU): Acts as the conductor of the computer orchestra. It fetches instructions sequentially from memory, decodes the operation code (opcode), coordinates micro-operations, and emits synchronized electrical timing and control signals to the ALU, registers, and system bus.
• CPU Internal Registers: Small, high-frequency internal memory cells running at processor clock speed:
  • Program Counter (PC): Holds the memory address of the next instruction scheduled to be fetched and executed. It automatically increments after each instruction fetch.
  • Memory Address Register (MAR): Holds the physical memory address currently being read from or written to across the address bus.
  • Memory Data Register (MDR) / Memory Buffer Register (MBR): Serves as a two-way staging buffer holding the data byte fetched from memory or prepared for writing into memory.
  • Instruction Register (IR): Holds the binary bit-pattern of the current instruction immediately after it is fetched from memory while the Control Unit decodes it.
  • Accumulator (ACC): A primary general-purpose arithmetic register that stores intermediate computational results produced by the ALU.

Every CPU operation proceeds through a cyclic four-step pipeline known as the FDE Cycle:

1. Fetch: The address in the PC is loaded into the MAR. The Control Unit asserts a Memory Read signal on the control bus. The memory returns the instruction byte via the data bus into the MDR. The contents of the MDR are copied into the IR. Concurrently, the PC is incremented ($PC \leftarrow PC + ext{instruction length}$) to point to the subsequent instruction.
2. Decode: The instruction in the IR is parsed by the CU's instruction decoder. The opcode determines which operation is required, and addressing modes specify whether operands reside in CPU registers, immediate constants, or memory addresses.
3. Execute: The CU signals the ALU or internal data paths to execute the operation (e.g., adding two register values or fetching an operand from RAM).
4. Store (Write-back): The result generated by the ALU is written back into the designated destination register (such as the Accumulator) or dispatched to primary memory.

A bus is a shared collection of parallel electrical conductor pathways connecting internal CPU components to memory and peripheral interfaces. System buses are segregated by their functional role:

• Data Bus: A bidirectional highway carrying actual raw data and instruction codes between the CPU, memory, and peripheral controllers. The width of the data bus (e.g., 32 bits, 64 bits) dictates the system's word size and maximum data throughput per bus clock cycle.
• Address Bus: A unidirectional highway driven exclusively by the CPU (or DMA controllers) to specify the physical destination address in memory or I/O ports. If an address bus contains $k$ physical lines, the processor can directly address exactly $2^k$ distinct memory locations (bytes). For example, a 32-bit address bus can address $2^{32} = 4,294,967,296 ext{ bytes} = 4 ext{ GB}$ of RAM.
• Control Bus: A collection of individual control and timing signal lines managing read/write direction, clock synchronization, reset, and hardware interrupt requests (e.g., MEMR, MEMW, IOR, IOW, INTR, RESET, CLK).

Modern computational efficiency depends fundamentally on the empirical observation known as the Principle of Locality of Reference. Programs do not access all memory locations uniformly; rather, memory accesses are clustered in time and space:

• Temporal Locality (Locality in Time): If a specific memory address is accessed once, there is a high probability that the exact same location will be accessed repeatedly in the near future (e.g., variables inside a loop, loop index counters).
• Spatial Locality (Locality in Space): If a specific memory address is accessed, memory locations immediately adjacent to it are likely to be accessed soon thereafter (e.g., contiguous elements in an array, sequential instruction execution).

Hardware designers structure computer memory in a hierarchical pyramid to achieve the ideal compromise between speed, capacity, and cost per bit:

Primary memory is directly accessible by the CPU over the system bus:

• RAM (Random Access Memory): Read/write volatile memory whose content is lost when electrical power is terminated. RAM is divided into two architectural implementations:
  • SRAM (Static RAM): Memory cells constructed from 4 to 6 transistor bistable flip-flops. Does not require periodic capacitive refreshing. Delivers blazing access speeds (nanoseconds), but consumes higher power and has lower storage density. Utilized primarily in processor caches.
  • DRAM (Dynamic RAM): Memory cells constructed from a single transistor and miniature capacitor (1T-1C). The capacitor leaks charge over time and must be refreshed periodically (hundreds of times per second) by dedicated memory controllers. Provides massive storage density and low manufacturing cost, serving as standard system RAM (DDR4, DDR5).
• ROM (Read-Only Memory): Non-volatile memory retaining data permanently without power. Stores the system firmware / BIOS (Basic Input/Output System) or UEFI responsible for executing the Power-On Self-Test (POST) and bootstrapping the operating system. ROM variants include:
  • MROM (Mask ROM): Hardwired during silicon fabrication; immutable and non-programmable.
  • PROM (Programmable ROM): Manufactured blank and programmed once using a specialized device (PROM burner) by melting internal microscopic fuses.
  • EPROM (Erasable Programmable ROM): Can be erased completely by exposing the silicon die to intense Ultraviolet (UV) light through a transparent quartz window, then reprogrammed.
  • EEPROM (Electrically Erasable PROM): Can be erased and rewritten byte-by-byte electrically without UV exposure. Forms the underlying technology for USB flash drives and modern Solid State Drives.

When the CPU requests a memory word, the hardware first queries the cache controller:

• Cache Hit: The requested word is present in cache memory. The word is supplied immediately at cache speed ($T_c$).
• Cache Miss: The requested word is absent from cache. A block of words containing the target address must be fetched from slower main memory ($T_m$), incurring a Miss Penalty.
• Hit Ratio ($H$): The fraction of total memory accesses that are resolved in cache: $H = rac{ ext{Cache Hits}}{ ext{Total Accesses}}$.
• Average Memory Access Time (AMAT): $T_{ ext{avg}} = T_c + (1 - H) imes T_m$. Even a modest 95% hit ratio ($H = 0.95$) reduces effective access latency from 60 ns down to under 5 ns.

Because primary memory is volatile and finite, secondary auxiliary storage preserves operating system files, application programs, and user data permanently:

• Magnetic Hard Disk Drive (HDD): Employs rapidly rotating circular magnetic platters (5400 or 7200 RPM) coated with ferromagnetic material. Read/write electromagnetic heads float on a cushion of air over concentric circular tracks divided into sectors (typically 512 bytes or 4096 bytes). Performance is limited by mechanical movement: Seek Time (time to position head over target track) + Rotational Latency (time for target sector to rotate beneath head).
• Solid State Drive (SSD): Eliminates all moving mechanical components by utilizing arrays of non-volatile NAND flash memory chips. Read and write operations occur purely electronically via flash memory controllers featuring wear-leveling algorithms. Modern NVMe (Non-Volatile Memory Express) SSDs communicate directly over high-speed PCIe lanes, achieving sequential read speeds exceeding 7000 MB/s compared to ~150 MB/s for mechanical HDDs.

In a positional number system with base (or radix) $r$, the numerical value represented by a string of digits is evaluated as the sum of each digit multiplied by its positional power of the base:

$$\text{Value} = \sum_{i=-m}^{n-1} d_i \cdot r^i = d_{n-1} r^{n-1} + \dots + d_1 r^1 + d_0 r^0 + d_{-1} r^{-1} + \dots + d_{-m} r^{-m}$$

The four primary number systems used in computer science are:

• Decimal (Base 10): Employs 10 symbols: $0, 1, 2, 3, 4, 5, 6, 7, 8, 9$.
• Binary (Base 2): Employs 2 symbols: $0, 1$. The fundamental language of digital circuitry.
• Octal (Base 8): Employs 8 symbols: $0, 1, 2, 3, 4, 5, 6, 7$. Exactly corresponds to 3-bit binary groupings ($2^3 = 8$).
• Hexadecimal (Base 16): Employs 16 symbols: $0-9$ followed by $A (10), B (11), C (12), D (13), E (14), F (15)$. Exactly corresponds to 4-bit binary groupings ($2^4 = 16$). Highly compact for representing memory addresses and byte values.

To convert a number from base $r$ to decimal (base 10), expand each digit by its positional weight $r^i$ and evaluate the arithmetic sum in decimal:

Converting decimal to base $r$ requires two distinct algorithms for the integer and fractional parts:

• Integer Part: Successive Division Method. Repeatedly divide the decimal integer by target base $r$, recording the integer quotient and the remainder. Terminate when the quotient becomes 0. The digits in base $r$ are read from bottom to top (Last Remainder = Most Significant Digit / MSD).
• Fractional Part: Successive Multiplication Method. Repeatedly multiply the fractional part by target base $r$, recording the resulting integer portion as the next digit. Retain the remaining fractional part for the next multiplication step. Read the extracted integer digits from top to bottom (First Integer = MSD of fraction).

Because $8 = 2^3$ and $16 = 2^4$, conversions between these bases require zero arithmetic division or multiplication—only direct bit grouping:

• Binary to Octal: Group binary bits in sets of 3 starting from the binary point moving left for integer digits (pad leading zeros if necessary) and moving right for fractional digits (pad trailing zeros). Replace each 3-bit group with its single octal digit equivalent ($000_2=0$ to $111_2=7$).
• Binary to Hexadecimal: Group binary bits in sets of 4 starting from the binary point moving left for integer digits and right for fractional digits. Replace each 4-bit nibble with its hexadecimal equivalent ($0000_2=0$ to $1111_2=F$).
• Octal to Hexadecimal: Convert each octal digit into its 3-bit binary equivalent first, regroup the resulting binary string into 4-bit nibbles, and substitute the corresponding hexadecimal characters.

Computers must represent both positive and negative values using purely binary bits. In an $n$-bit register, three representation conventions exist:

• Sign-Magnitude: The Most Significant Bit (MSB, bit $n-1$) serves as the sign indicator ($0 = \text{positive}$, $1 = \text{negative}$), while the remaining $n-1$ bits encode the true binary magnitude. Flaws: Dual representation of zero ($+0 = 00000000_2$ and $-0 = 10000000_2$ in 8 bits), requiring cumbersome and slow hardware checks.
• 1's Complement: Positive numbers are represented identically to standard binary. A negative number is formed by taking the bitwise logical NOT of its positive counterpart (inverting all 0s to 1s and 1s to 0s). Flaws: Also suffers from dual zero ($+0 = 00000000_2$ and $-0 = 11111111_2$) and requires an "end-around carry" during addition.
• 2's Complement: The undisputed universal standard in modern CPU ALUs. A negative number is formed by adding 1 to its 1's complement: $\text{2's Complement} = \text{1's Complement} + 1$.

2's complement offers two immense hardware engineering benefits:

1. Unique Zero: There is only one zero representation ($00000000_2$). Taking the 2's complement of 0 yields: $1\text{'s comp} = 11111111_2 + 1 = 100000000_2$. In an 8-bit register, the 9th bit carries out and is discarded, leaving $00000000_2$.
2. Subtraction via Standard Addition Circuitry: Subtraction $A - B$ is executed directly as $A + (\text{2's complement of } B)$. The ALU does not require an independent subtractor circuit—the same adder handles signed addition and subtraction seamlessly.

The dynamic range of values represented in an $n$-bit 2's complement system is:

$$\text{Range} = [-2^{n-1}, +2^{n-1} - 1]$$

For an 8-bit byte: $[-2^7, +2^7 - 1] = [-128, +127]$. For a 16-bit word: $[-32768, +32767]$. For a 32-bit integer: $[-2,147,483,648, +2,147,483,647]$.

An overflow occurs when the mathematical result of an arithmetic operation exceeds the finite representable range of the register. In signed 2's complement arithmetic:

• Adding two numbers of opposite signs can never produce an overflow.
• Adding two positive operands that yields an apparently negative result (MSB = 1) signifies a positive overflow.
• Adding two negative operands that yields an apparently positive result (MSB = 0) signifies a negative overflow.
• Hardware Detection Rule: Overflow occurs if and only if the carry generated into the sign bit position ($C_{\text{in}}$) does not equal the carry generated out of the sign bit position ($C_{\text{out}}$): $V = C_{\text{in}} \oplus C_{\text{out}} = 1$.

Computers represent alphanumeric characters and symbols using standardized numeric codes:

• ASCII (American Standard Code for Information Interchange): Developed in 1963. Standard ASCII uses 7 bits to encode $2^7 = 128$ distinct characters (codes 0 to 127), including uppercase letters ('A' = 65 to 'Z' = 90), lowercase letters ('a' = 97 to 'z' = 122), digits ('0' = 48 to '9' = 57), and control characters (LF = 10, CR = 13). Extended ASCII uses 8 bits (256 codes) to support graphical box characters and Western European diacritics.
• ISCII (Indian Script Code for Information Interchange): An 8-bit encoding standard established by the Bureau of Indian Standards (BIS) in 1991. The lower 128 characters mirror standard 7-bit ASCII, while the upper 128 positions encode phonetically unified characters across Indian scripts (Bengali, Devanagari, Gurmukhi, Gujarati, Oriya, Tamil, Telugu, Kannada, Malayalam).
• Unicode: A universal character encoding standard capable of representing every written script on Earth, ancient symbols, mathematical notation, and emojis. It defines a code space of over 1.1 million code points ($U+0000$ to $U+10FFFF$). Popular serialization encodings include:
  • UTF-8: Variable-length encoding using 1 to 4 bytes per character. 100% backward-compatible with 7-bit ASCII (uses 1 byte for ASCII 0-127). The dominant standard of the global World Wide Web.
  • UTF-16: Variable-length encoding using one or two 16-bit code units (2 or 4 bytes). Standard in Java, JavaScript runtime engines, and Windows internal APIs.
  • UTF-32: Fixed-length encoding allocating exactly 4 bytes (32 bits) per character, enabling fast $O(1)$ indexing at the cost of high memory consumption.

Formulated by English mathematician George Boole in 1854, Boolean algebra operates over binary variables taking values from the set $\{0, 1\}$. The fundamental axioms and operational laws are summarized below:

The Principle of Duality states that any valid Boolean identity remains strictly valid if:

• All AND operators ($\ hecdot$) are replaced by OR operators ($+$), and vice versa.
• All identity elements ($0$ and $1$) are interchanged ($0 \leftrightarrow 1$).
• Variables and their complemented forms remain unchanged.

De Morgan's theorems establish the algebraic relationship between logical addition and logical multiplication under inversion:

• First Theorem: The complement of a logical sum is equal to the logical product of individual complements:$$\overline{A + B} = \overline{A} \cdot \overline{B}$$
• Second Theorem: The complement of a logical product is equal to the logical sum of individual complements:$$\overline{A \cdot B} = \overline{A} + \overline{B}$$

A logic gate is an idealized physical electronic circuit implementing a Boolean operation:

• Basic Gates:
  • NOT Gate (Inverter): Single input, single output. Output is $Y = \overline{A}$.
  • AND Gate: Output is HIGH ($1$) only when ALL inputs are HIGH: $Y = A \cdot B$.
  • OR Gate: Output is HIGH ($1$) when AT LEAST ONE input is HIGH: $Y = A + B$.
• Universal Gates (NAND & NOR): A gate is classified as universal if any arbitrary Boolean function, combinational logic circuit, or fundamental gate (NOT, AND, OR) can be constructed exclusively using that single gate type.
  • NAND Gate: AND followed by NOT: $Y = \overline{A \cdot B}$. Output is LOW only when all inputs are HIGH.
  • NOR Gate: OR followed by NOT: $Y = \overline{A + B}$. Output is HIGH only when all inputs are LOW.
• Special Purpose Arithmetic Gates:
  • XOR Gate (Exclusive-OR): Output is HIGH when an odd number of inputs are HIGH (for two inputs, when inputs differ): $Y = A \oplus B = \overline{A}B + A\overline{B}$. Forms the foundation of binary half adders and parity generators.
  • XNOR Gate (Equivalence / Exclusive-NOR): Output is HIGH when inputs are identical: $Y = \overline{A \oplus B} = AB + \overline{A}\,\overline{B}$.

Every Boolean truth function can be represented uniquely in standard canonical form:

• Minterms ($m_i$) and SOP Form: A minterm is a product (AND) of all literal variables in either true or complemented form. A literal is complemented if the variable is 0, and uncomplemented if 1. The canonical Sum of Products (SOP) is the logical OR of all minterms for which the function output is 1: $F(A,B,C) = \sum m(1, 3, 5, 7)$.
• Maxterms ($M_i$) and POS Form: A maxterm is a sum (OR) of all literal variables in either true or complemented form. A literal is uncomplemented if the variable is 0, and complemented if 1. The canonical Product of Sums (POS) is the logical AND of all maxterms for which the function output is 0: $F(A,B,C) = \prod M(0, 2, 4, 6)$.

Computer software constitutes the collection of programs, procedures, and documentation executing computational instructions on physical hardware. Software is partitioned into two major domains:

• System Software: Low-level software that directly manages hardware resources, provides core platform infrastructure, and isolates application developers from physical hardware complexities. Includes Operating Systems, Language Translators, Device Drivers, and System Utilities.
• Application Software: High-level software designed to fulfill specific user tasks and problem-solving workflows. Subdivided into:
  • General Purpose: Broadly applicable packages such as office suites, web browsers, media players, and CAD software.
  • Custom / Bespoke Software: Tailored software engineered to fulfill the unique requirements of a particular organization, such as a school ERP portal, hospital inventory system, or bank core transaction engine.

Because microprocessors only execute native machine code (binary 0s and 1s), language translators convert human-readable source code into machine-executable binary:

The software build pipeline involves two additional vital system programs:

• Linker: Takes one or more compiled object files produced by the compiler along with pre-compiled system library modules (e.g., standard I/O, math libraries) and resolves external cross-references, combining them into a single coherent executable binary file.
• Loader: A core component of the operating system that reads the executable file from secondary storage (SSD/HDD), allocates physical address space in RAM, binds relative addresses, initializes register state, and transfers CPU control to the program's entry point (`main`).

An Operating System (OS) acts as the resource manager of the computer, providing an abstraction layer (APIs and System Calls) over raw physical hardware:

1. Processor / Process Management: A process is a program in execution. The OS creates, schedules, synchronizes, and terminates processes. CPU scheduling algorithms include First-Come-First-Served (FCFS), Shortest Job First (SJF), Priority Scheduling, and Round Robin (RR) with time quantum slices.
2. Memory Management: Dynamically allocates and deallocates memory blocks. Uses Virtual Memory via demand paging, where programs can execute even if they exceed physical RAM capacity. The OS maintains page tables translating virtual addresses to physical frame addresses and manages page swaps between RAM and disk swap space.
3. File System Management: Manages files organized in a hierarchical tree directory structure. Regulates read/write access permissions, directory navigation, and physical storage mapping across file system formats (e.g., NTFS, ext4, FAT32).
4. Device / I/O Management: Provides uniform device drivers and shields the application from hardware idiosyncrasies. Uses Buffering (temporary memory holding data during transfer) and SPOOLing (Simultaneous Peripheral Operations On-Line), where print jobs or slow I/O tasks are queued on disk so the high-speed CPU is not bottlenecked.
5. Security and Protection: Controls user authentication, role-based privileges, and prevents unauthorized memory accesses between isolated processes.

• Single-User Single-Tasking: Only one user can execute one program at a time (e.g., MS-DOS).
• Single-User Multi-Tasking: A single user can run multiple programs concurrently (e.g., Windows 11, macOS).
• Multi-User Time-Sharing: Multiple users log in simultaneously across terminals, sharing CPU time slices (e.g., Linux, UNIX).
• Real-Time Operating Systems (RTOS): Guarantees deterministic, strict deadline response times. Divided into Hard RTOS (missing a deadline results in catastrophic failure, e.g., missile guidance, aircraft avionics, pacemaker) and Soft RTOS (deadline miss degrades quality but causes no catastrophe, e.g., video streaming).
• Distributed OS: Coordinates a collection of independent, networked computers appearing to users as a single unified system.