Electronic Devices

In an isolated single atom, electrons occupy sharp, discrete quantum energy levels governed by the Pauli exclusion principle. However, when N identical atoms assemble closely into a periodic crystal lattice (with interatomic spacing typically 2 - 3 Å), the outer valence electron wavefunctions overlap strongly. Under the influence of the periodic Coulomb potential of neighboring ionic cores, each discrete atomic energy level splits into N closely spaced sub-levels. Because N ≈ 10²⁸ atoms/m³, these sub-levels form a continuous quasi-continuous continuum termed an Energy Band.

The two most critical energy bands governing electrical conduction are:

• Valence Band (VB): The highest occupied energy band formed by the outermost valence electrons. At absolute zero (0 K), the valence band is completely packed with electrons and cannot contribute to electric conduction under an external electric field.
• Conduction Band (CB): The lowest unoccupied or partially filled energy band lying immediately above the valence band. Electrons excited into this band are quasi-free to accelerate in response to an electric field, carrying electrical current.
• Forbidden Energy Gap (E_g): The forbidden energy range separating the top of the valence band (E_v) and the bottom of the conduction band (E_c). No quantum electron states are allowed within this band gap: E_g = E_c - E_v.

In metals, electrical resistance increases linearly with temperature (α > 0, positive temperature coefficient) due to increased thermal lattice phonon vibrations scattering free electrons. Conversely, in semiconductors, as temperature rises from absolute zero, thermal energy breaks covalent bonds, exciting valence electrons across E_g into the conduction band and creating mobile electron-hole pairs. Consequently, charge carrier concentration increases exponentially:

Thus, semiconductors possess a negative temperature coefficient of resistance (α < 0): their electrical conductivity increases rapidly with increasing temperature.

An intrinsic semiconductor is an ultra-pure crystal of tetravalent elements (such as Silicon, Z = 14, or Germanium, Z = 32) without any intentional impurities. In the diamond cubic crystal lattice, each Si atom shares its 4 valence electrons with 4 neighboring Si atoms to form 4 strong covalent bonds.

• At T = 0 K: All valence electrons are tightly locked in covalent bonds (VB completely filled, CB completely empty). The crystal acts as an ideal insulator.
• At T > 0 K: Thermal energy ruptures a small fraction of covalent bonds, liberating free electrons into the conduction band. The vacancy left behind in the valence band behaves as an effective positive charge carrier of charge +e, termed a Hole.
• Carrier Equality: Electrons and holes are generated strictly in pairs, hence the electron concentration n_e equals the hole concentration n_h, equal to the intrinsic concentration n_i:
  n_e = n_h = n_i
  (For pure Si at 300 K, n_i ≈ 1.5 × 10¹⁶ m⁻³).
• Total Conduction Current: Both electrons in CB and holes in VB contribute additively to current:
  I = I_e + I_h = e · A · [ n_e · v_e + n_h · v_h ] = e · A · E · [ n_e · μ_e + n_h · μ_h ]
  Where μ_e and μ_h are electron and hole mobilities (with μ_e > μ_h because electrons in CB move in vacant space, whereas holes move via sequential valence bonding jumps).

The intrinsic carrier concentration of pure Si is too low for practical device manufacturing. Doping is the deliberate addition of a tiny, controlled quantity of specific impurity atoms (typically 1 part in 10⁶ to 10⁸ host atoms) into the pure semiconductor lattice to dramatically multiply its electrical conductivity.

1. n-Type Semiconductor (Pentavalent Doping):

• Dopants: Group 15 pentavalent donor atoms—Phosphorus (P), Arsenic (As), Antimony (Sb).
• Mechanism: Four of the five valence electrons participate in covalent bonding with neighboring Si atoms. The fifth electron is weakly bound (binding energy ~ 0.05 eV in Si) and easily ionizes into the conduction band at room temperature, leaving behind an immobile positive donor ion (N_d⁺).
• Carrier Densities: Electrons are majority carriers; holes are minority carriers:
  n_e ≈ N_d >> n_h
• Donor Level: The discrete donor energy level E_d lies just below the bottom of the conduction band (~ 0.045 eV below E_c).

2. p-Type Semiconductor (Trivalent Doping):

• Dopants: Group 13 trivalent acceptor atoms—Boron (B), Aluminum (Al), Indium (In), Gallium (Ga).
• Mechanism: The three valence electrons bond with three adjacent Si atoms, leaving one bond deficient of an electron. A neighboring valence electron easily hops in to satisfy the bond, creating a mobile hole in the valence band and leaving behind an immobile negative acceptor ion (N_a⁻).
• Carrier Densities: Holes are majority carriers; electrons are minority carriers:
  n_h ≈ N_a >> n_e
• Acceptor Level: The discrete acceptor energy level E_a lies just above the top of the valence band (~ 0.045 eV above E_v).

When donor atoms are added to create an n-type semiconductor, the enormous excess of electrons increases the rate of recombination with holes, suppressing the equilibrium hole concentration n_h = n_i² / n_e far below the intrinsic level.

Crucial Examination Fact: Despite having excess free electrons or holes, an extrinsic semiconductor (n-type or p-type) remains 100% electrically neutral, because the positive charge of ionized donors/holes is exactly balanced by the negative charge of electrons/acceptor ions:

When a p-type semiconductor and an n-type semiconductor are metallurgically fused into a single monolithic crystal, two simultaneous carrier transport processes commence immediately:

1. Diffusion Process: Driven by the enormous carrier concentration gradient, majority holes from the p-region diffuse across the interface into the n-region, while majority electrons from the n-region diffuse into the p-region.
2. Depletion Region (Space-Charge Layer): Recombination of diffusing electrons and holes near the junction uncovers uncompensated immobile donor ions (+q) on the n-side and uncompensated immobile acceptor ions (-q) on the p-side. This narrow region (thickness W ≈ 0.1 - 1 μm) devoid of free mobile carriers is called the Depletion Region.
3. Built-in Barrier Potential (V₀): The unneutralized space-charge ions establish an internal electric field directed from the n-side to the p-side. This field opposes further majority carrier diffusion while encouraging minority carrier drift. Diffusion and drift currents reach dynamic equilibrium, creating an electrostatic Barrier Potential:
   V₀ ≈ 0.7 V for Silicon (Si) at 300 K; V₀ ≈ 0.3 V for Germanium (Ge).

1. Forward Bias:

• The p-region is connected to the positive terminal of an external DC voltage source, and the n-region is connected to the negative terminal.
• The applied forward voltage V_F opposes the built-in barrier field, lowering the effective barrier height to (V₀ - V_F).
• The depletion width W contracts significantly. When V_F exceeds the Knee (Cut-in) Voltage (0.7 V for Si, 0.3 V for Ge), majority carriers easily surmount the reduced barrier, causing the forward current I_F to rise exponentially (measured in milliamperes, mA).
• Dynamic Forward Resistance: r_f = ΔV_F / ΔI_F (typically 10 - 50 Ω).

2. Reverse Bias:

• The p-region is connected to the negative terminal, and the n-region to the positive terminal.
• The applied reverse voltage V_R aids the built-in barrier field, raising the effective barrier height to (V₀ + V_R).
• The depletion width expands drastically, completely choking majority carrier diffusion.
• Only thermally generated minority carriers (electrons in p-side, holes in n-side) are swept across the junction by the electric field, yielding an extremely tiny Reverse Saturation Current (I_s), measured in microamperes (μA) in Ge and nanoamperes (nA) in Si. I_s is independent of reverse voltage but doubles every ~10 °C rise in temperature.
• Dynamic Reverse Resistance: r_r = ΔV_R / ΔI_R (extremely high, typically ~ 1 MΩ).

A rectifier is an electrical circuit that converts alternating current (AC) into pulsating direct current (DC) by exploiting the unidirectional conduction property of p-n junction diodes.

The pulsating output of a rectifier contains both an intended DC component and unwanted AC ripples. Connecting a large capacitor C in shunt across the load resistance R_L smooths the output: the capacitor charges rapidly to V_m during diode conduction and discharges slowly through R_L with a large time constant τ = R_L · C when the diode shuts off. The ripple factor with a shunt capacitor filter reduces to:

A Zener Diode is a heavily doped silicon p-n junction diode designed specifically to operate continuously in the reverse breakdown region without damage. In breakdown, the terminal voltage remains virtually rock-solid at the Zener breakdown voltage V_z over a wide range of reverse current (from knee current I_{z, ext{min}} to maximum rated current I_{z, ext{max}}).

• Circuit Configuration: The unregulated DC input V_i is connected across the Zener diode in reverse bias with a series current-limiting resistor R_s, and the load R_L is connected in parallel with the Zener.
• Regulation Mechanism:
  V_o = V_z = ext{constant}
  Input voltage equation: V_i = I_s · R_s + V_z = (I_z + I_L) · R_s + V_z
  If input voltage V_i increases, the excess voltage drops across R_s as Zener current I_z rises, leaving V_o unchanged.
• Design Equation: R_s = (V_{i, ext{min}} - V_z) / (I_{L, ext{max}} + I_{z, ext{min}}).

1. Light Emitting Diode (LED):
   Operated in forward bias. Electrons injected into the p-side recombine with holes, releasing quantum transition energy as emitted photons: hν = E_g ⟹ λ = hc / E_g ≈ 1240 / E_g( ext{eV}) ext{ nm}. For visible light emission (400 - 700 nm), the semiconductor bandgap must satisfy E_g ≥ 1.8 eV (e.g., Gallium Arsenide Phosphide, GaAs_{1-x}P_x, or Indium Gallium Nitride, InGaN). Silicon cannot be used for LEDs because it is an indirect bandgap material where recombinations release heat phonons rather than photons.
2. Photodiode:
   Operated in reverse bias. Incident photons with energy hν ≥ E_g penetrate the depletion region, generating electron-hole pairs. The built-in field sweeps electrons to the n-side and holes to the p-side, producing a reverse photocurrent proportional to light intensity (I_{ ext{rev}} \propto \Phi).
   Why Reverse Biased? In reverse bias, the dark current is governed by tiny minority carriers (I_0). When illuminated, a moderate change in carrier generation yields a huge fractional change (ΔI / I_0 >> 1), making detection orders of magnitude more sensitive than in forward bias where huge majority carrier background obscures the signal.
3. Solar Cell (Photovoltaic Device):
   An unbiased large-area p-n junction that converts optical solar radiation into electrical power. The operational sequence involves three steps:
   (1) Generation of e-h pairs by solar photons near the junction, (2) Separation of electrons and holes by the internal built-in field before recombination, and (3) Collection at top finger electrodes and bottom metallic back-contact.
   The I-V characteristic operates in the fourth quadrant because the solar cell supplies electrical power to an external load (Open-circuit voltage V_{oc} ≈ 0.6 V, Short-circuit current I_{sc}).

A Bipolar Junction Transistor (BJT) is a three-terminal, two-junction active semiconductor device consisting of three sequentially doped regions:

• Emitter (E): Heavily doped, moderate physical size. Its sole function is to inject huge quantities of majority carriers into the base.
• Base (B): Extremely thin (typically ~ 1 μm) and very lightly doped. It serves as a transit bridge, allowing more than 95 - 99% of injected carriers to pass through to the collector without recombination.
• Collector (C): Moderately doped, largest physical dimensions to efficiently dissipate thermal heat produced during carrier collection.

Active Biasing Rule: For proper amplification action, the Emitter-Base (E-B) junction must be Forward Biased, and the Collector-Base (C-B) junction must be Reverse Biased.

Applying Kirchhoff's Current Law to the transistor package yields the fundamental current equation:

Typically, base current I_B is only 1 - 5% of I_E (measured in μA), while collector current I_C is 95 - 99% of I_E (measured in mA).

Current Amplification Factors:

• Common Base (CB) Current Gain (α):
  α = I_C / I_E (or ΔI_C / ΔI_E at constant V_{CB}). Practical range: 0.95 ≤ α ≤ 0.995.
• Common Emitter (CE) Current Gain (β):
  β = I_C / I_B (or ΔI_C / ΔI_B at constant V_{CE}). Practical range: 20 ≤ β ≤ 300.
• Mathematical Relations between α and β:
  Dividing I_E = I_B + I_C by I_C: 1/α = 1/β + 1 ⟹ β = α / (1 - α) and α = β / (1 + β).

1. Input Characteristic: Plot of base current I_B versus base-emitter voltage V_{BE} at fixed collector-emitter voltage V_{CE}. Resembles a forward-biased diode curve with threshold voltage ~ 0.7 V for Si.
Dynamic Input Resistance: r_i = ( ΔV_{BE} / ΔI_B )_{V_{CE}} (typically 500 Ω - 2 kΩ).

2. Output Characteristic: Plot of collector current I_C versus collector-emitter voltage V_{CE} at fixed base current I_B. Three distinct operating regions exist:

• Active Region: E-B forward biased, C-B reverse biased. I_C is almost independent of V_{CE} (curves are nearly horizontal). Used for linear amplifier circuits.
• Saturation Region: Both E-B and C-B junctions are forward biased. V_{CE} < 0.2 V (transistor ON state, closed switch).
• Cut-off Region: Both E-B and C-B junctions are reverse biased. I_B = 0, I_C ≈ 0 (transistor OFF state, open switch).

In a common-emitter amplifier, the input AC signal v_{in} is superposed on the base-emitter DC bias, and output voltage v_o is taken from the collector across load resistor R_L.

• Applying Kirchhoff's Voltage Law to the collector loop:
  V_{CC} = I_C · R_L + V_{CE} ⟹ V_{CE} = V_{CC} - I_C · R_L
• The 180° Phase Reversal:
  During the positive half-cycle of input voltage v_{in}, forward bias V_{BE} increases ⟹ I_B increases ⟹ I_C = β I_B increases ⟹ voltage drop I_C · R_L across load resistor increases ⟹ output voltage V_{CE} = V_{CC} - I_C R_L decreases (becomes more negative).
  Conversely, during the negative half-cycle of v_{in}, I_C decreases, causing output V_{CE} to increase. Thus, the output signal is amplified and 180° (π radians) out of phase with the input signal.
• Amplification Formulas:
  Voltage Gain: A_v = v_o / v_{in} = - ( ΔI_C · R_L ) / ( ΔI_B · r_i ) = - β · ( R_L / r_i ) = - g_m · R_L (where g_m = β / r_i is transconductance).
  Power Gain: A_p = A_v · β = β² · ( R_L / r_i ).

In electronic systems, signals are categorized into two fundamental domains:

• Analog Signal: A continuous voltage or current waveform that takes on an infinite continuum of values over time (e.g., audio microphone output, sinusoidal AC power, thermal sensor voltage).
• Digital Signal: A discontinuous signal that assumes only two discrete voltage levels:
  Logic 0 (LOW): Binary 0, typically representing 0 V to 0.8 V.
  Logic 1 (HIGH): Binary 1, typically representing 2.4 V to 5.0 V.

1. NOT Gate (Inverter):
   A single-input, single-output gate that inverts the logic state.
   Boolean Equation: Y = Ā (Y equals NOT A).
   Truth Table: A = 0 ⟹ Y = 1; A = 1 ⟹ Y = 0.
   Electronic Realization: A transistor operated in common-emitter saturation/cut-off mode.
2. OR Gate:
   A multi-input gate whose output is 1 if any one or more inputs are 1. Output is 0 only when all inputs are 0.
   Boolean Equation: Y = A + B (Logical Addition).
   Truth Table: (0,0) → 0 | (0,1) → 1 | (1,0) → 1 | (1,1) → 1.
   Electronic Realization: Two parallel forward-biased diodes connected to a pull-down resistor.
3. AND Gate:
   A multi-input gate whose output is 1 if and only if all inputs are simultaneously 1.
   Boolean Equation: Y = A · B (Logical Multiplication).
   Truth Table: (0,0) → 0 | (0,1) → 0 | (1,0) → 0 | (1,1) → 1.
   Electronic Realization: Two diodes connected in reverse configuration to a pull-up resistor.

A Universal Gate is a logic gate that can implement any arbitrary Boolean function (including NOT, AND, OR, XOR) without requiring any other type of gate. Both NAND and NOR are universal gates.

1. NAND Gate (NOT-AND):

• Boolean Equation: Y = (A · B)̄
• Truth Table: (0,0) → 1 | (0,1) → 1 | (1,0) → 1 | (1,1) → 0.
• Synthesis of Basic Gates using only NAND:
  • NOT Gate: Tie both inputs together: Y = (A · A)̄ = Ā (Requires 1 NAND).
  • AND Gate: Feed NAND output into a NAND-inverter: Y = [ (A · B)̄ ]̄ = A · B (Requires 2 NANDs).
  • OR Gate: Invert inputs and feed to NAND: Y = (Ā · B̄)̄ = Ā̄ + B̄̄ = A + B (Requires 3 NANDs).

2. NOR Gate (NOT-OR):

• Boolean Equation: Y = (A + B)̄
• Truth Table: (0,0) → 1 | (0,1) → 0 | (1,0) → 0 | (1,1) → 0.
• Synthesis of Basic Gates using only NOR:
  • NOT Gate: Tie both inputs together: Y = (A + A)̄ = Ā (Requires 1 NOR).
  • OR Gate: Invert NOR output: Y = [ (A + B)̄ ]̄ = A + B (Requires 2 NORs).
  • AND Gate: Invert inputs and feed to NOR: Y = (Ā + B̄)̄ = Ā̄ · B̄̄ = A · B (Requires 3 NORs).

De Morgan's laws form the mathematical basis for hardware gate minimization in modern digital logic design and VLSI microprocessor compilation.